TI DAC7625: Quad Parallel DAC with Zero-Scale Reset | Texas Instruments

DAC7625 contains four 12-bit voltage-output DACs with a twelve-bit parallel data interface. Double-buffered registers allow software or logic to prepare channel values before applying a coordinated update. This architecture suits multi-channel setpoints where loading channels sequentially should not immediately change each analog output.

The reset distinction from DAC7624 is consequential: DAC7625 clears its registers to code 000H, whereas DAC7624 uses midscale code 800H. Zero code is not necessarily zero volts. The low and high reference inputs define the transfer span, so a bipolar configuration can reset DAC7625 toward its negative reference endpoint.

The device also supports readback of its input registers. That confirms digital register contents, not the measured analog output or successful settling into an external load. Check read/write timing, LDAC sequencing and output settling separately. The documented supply arrangements are single +5 V or +5 V/−5 V, with the chosen reference and output range constrained accordingly.